This invention relates to a drive circuit implemented by an MOS (metal-oxide-semiconductor) integrated circuit for driving a load circuit, such as an LSI (large scale integrated circuit).
Such a drive circuit is connected between a gate circuit, such as an AND gate circuit, and the load circuit. The gate circuit produces a gate output signal having one of gate circuit logic one and zero levels. The gate output signal has an insufficient current value to drive the load circuit with a required driving current. The drive circuit serves as a converting circuit for converting the gate output signal into a voltage signal so that the load circuit is driven by the required driving current. Furthermore, the drive circuit serves as a buffer circuit for preventing an adverse influence to which the load circuit would otherwise subject the gate circuit in operation thereof.
The drive circuit comprises an input terminal connected to the gate circuit and an output terminal. The load circuit is connected to the output terminal. The drive circuit is supplied with the gate output signal through the input terminal as an input signal having one of input signal logic one and zero levels.
As will later be described more in detail, the drive circuit further comprises an inverter connected to the input terminal and a p-channel and an n-channel MOS transistor. The inverter inverts the input signal and produces an inverted signal having inverted signal logic zero and logic one levels when the input signal has the input signal logic one and the logic zero levels, respectively. The p-channel MOS transistor has a first gate terminal connected to the inverter, a first source terminal connected to a power supply having a predetermined positive voltage through a power supply line, and a first drain terminal connected to the output terminal. The n-channel type MOS transistor has a second gate terminal connected to the inverter, a second source terminal which is grounded through a ground line, and a second drain terminal connected to the output terminal.
The power supply is connected to a different power supply line connected to a different gate circuit. The second source terminal has a ground potential.
The p-channel MOS transistor is put into a first source-drain conductive state when the inverted signal has the inverted signal logic zero level. The n-channel MOS transistor is put into a second source-drain conductive state when the inverted signal has the inverted signal logic one level. As a result, the predetermined positive voltage is supplied to the load circuit through the output terminal when the input signal has the input signal logic one level. On the contrary, the ground potential is supplied to the load circuit when the input signal has the input signal logic zero level.
In such a drive circuit, a transition state occurs when the input signal changes from one of the input signal logic one and zero levels to another of the input signal one and zero levels. In the transition state, both of the p-channel and the n-channel MOS transistors are simultaneously and instantaneously put into the first and the second source-drain conductive state, respectively. In this moment, a current flows with a large current value from the power supply line to the ground line through the p-channel and the n-channel MOS transistors. This means that the drive circuit has an increased power consumption. Furthermore, the large current generates noise in the different power supply line. The noise causes miss-operation in the different gate circuit.